Accelerate debug, validation and optimization of complex multi-core Systems on Chip (SoCs) by leveraging embedded non-intrusive instrumentation. You can then observe what’s happening in the design when software runs on the system.
Accelerate the debugging, validation and optimization of complex multicore SoCs. Debug and software engineers can leverage embedded non-intrusive instrumentation such as bus monitors, network on chip (NoC) monitors and CPU debug modules. This allows them to observe the design when operational software runs on the system. The instruments enable complete transaction-level traffic visibility on buses with a wide range of measurements, analytics and statistics gathering. These tools are all highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The instrumentation is accessed through standard interfaces such as JTAG, USB2 or USB3.
Software provides much of the functionality of a broad spectrum of devices and systems. Software quality – and how the software interacts with the hardware it runs – is paramount.
The complexity of modern SoCs demands a system-wide approach to debug, validation & optimization. Tessent UltraSight is a scalable solution that integrates on-chip embedded hardware functional monitor IPs with a host-based SDK and a functional monitoring system builder tool, a combination that provides actionable visibility into a system's behavior under real software loads, accelerating time-to-market.
Get updated on the major trends affecting the technology industries. You will learn how Tessent Embedded Analytics can help optimize SoC performance, turning complexity into a competitive advantage.
Watch as Peter Claydon, president of Picocom explains how Tessent Embedded Analytics provides non-intrusive monitoring and insights used to optimize Picocom’s 5G small cell network SoCs.
Discover how Tessent UltraSight can be used to perform system-wide functional monitoring, in this demo including examples of using bus monitor traces for memory content mapping & bus performance.
Learn how the Tessent UltraSight EA Builder tool can generate a debug, trace & functional monitoring subsystem. EA Builder also allows the management of IP parameters and interfaces.
View this demonstration of detecting transactions that occur within a specified memory range.
Learn how a bus monitor is used to determine the average time of a bus transaction to trigger a capture of bus trace.
See how a bus monitor is configured to trigger other Tessent Embedded Analytics modules in the event of a timeout.
