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Tessent Embedded Analytics

Tessent UltraSight

Accelerate debug, validation and optimization of complex multi-core Systems on Chip (SoCs) by leveraging embedded non-intrusive instrumentation. You can then observe what’s happening in the design when software runs on the system.

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Accelerate debug, validation and optimization

Accelerate the debugging, validation and optimization of complex multicore SoCs. Debug and software engineers can leverage embedded non-intrusive instrumentation such as bus monitors, network on chip (NoC) monitors and CPU debug modules. This allows them to observe the design when operational software runs on the system. The instruments enable complete transaction-level traffic visibility on buses with a wide range of measurements, analytics and statistics gathering. These tools are all highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The instrumentation is accessed through standard interfaces such as JTAG, USB2 or USB3.

Case Study

How Picocom optimizes 5G SoCs and networks with Tessent

Listen to Peter Claydon, president of Picocom, along with Gajinder Panesar of Siemens explain how Tessent Embedded Analytics provides non-intrusive monitoring and insights used to optimize Picocom’s 5G small cell network SoCs.

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White Paper

SoC debug: The need for visibility

Software provides much of the functionality of a broad spectrum of devices and systems. Software quality – and how the software interacts with the hardware it runs – is paramount.

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White Paper

Optimizing SoC performance with Embedded Analytics

Get updated on the major trends affecting the technology industries. You will learn how Tessent Embedded Analytics can help optimize SoC performance, turning complexity into a competitive advantage.

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Electronic chip

Boost SoC debug/optimization using embedded software

Discover how embedded software can provide a superior alternative to extracting insights out of on-chip monitors

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Fact Sheet
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UVM Verification IP

Learn about our UVM verification IP test environment. It contains sequence libraries and integration tests to help carry out system-level verification of the Tessent IP deployed within an SoC.