A sign-off constraints platform provides demotion, budgeting and hierarchical equivalency of timing constraints at any stage of the ASIC or FPGA flow. Constraints certifier provides comprehensive capabilities to validate constraints and timing exceptions with respect to underlying HDL.
Constraints Certifier uses formal algorithms to verify the timing constraints, thus providing accurate in-depth analysis of both the design and its associated timing constraints. Using a formal engine to analyze the behavior of the design and the SDC files reduces noise and false warnings associated with static checking methods. Designers can generate incremental SDC in case the original SDC is missing constraints. When dealing with designer intent in the associated SDC file, SVAs can capture the requirements for further simulation for precise results.
Constraints Certifier empowers designers to perform constraints demotion and hierarchical budgeting based on percentages, delay or logic levels. Designers can visually debug failing paths and take corrective action via budget-map.
As constraints change, timing constraints may be inequivalent and lose original intent. TEC ensures block and top-level constraints are all in-context. Designers can also compare various versions of design and constraints.
Through use of SVA’s, designers can not only capture and validate timing intent of the design as defined in timing constraints files but also reduce the need for gate level simulation and challenges of setting up such analysis.