3D IC design solutions

3D IC design is a new design paradigm driven by the diminishing returns of IC technology scaling. 3D IC design leverages new advanced packaging technologies that enable the integration of one or more chiplets into a single package. Chiplets are integrated circuits (IC) optimized for integration into a single package.

3D IC designs require the seamless integration of multi-domain ECAD/MCAD tools within a highly integrated, design platform, referred to as 3D IC workflows. Leveraging Siemens’ broad portfolio of leading EDA and MCAD tools, a comprehensive set of workflows are offered spanning the spectrum from system level decomposition to manufacturing handoff to empower its customers to design these complex, chiplet-based designs.

The 3D IC workflows also require tight integration with a comprehensive set of design kits to enable the design, integration, and assembly of chiplet-based 3D IC designs. To enable a chiplet ecosystem, Siemens has taken leadership in driving the new CDX/OCP 3D IC Design Kits (3DK) initiatives in collaboration with other EDA vendors. Siemens is sponsoring and actively driving the adoption of these new industry standards by the JEDEC industry standards body and is committed to formally adopting these new standards in its tools and workflows.

3D IC design integrates multiple dies, such as logic and memory, into a single system using vertical stacking (e.g., TSVs) or advanced packaging technologies. It involves partitioning functionality into chiplets, defining die-to-die interconnects, and optimizing system PPA & cost. Unlike traditional 2D SoC design, 3D IC design requires system-level verification of connectivity, signal and power integrity, thermal behavior, and mechanical stress across the full stack. As Moore’s Law slows down, 3D IC design is critical to enabling higher performance, bandwidth, and energy efficiency to meet AI / HPC application demands.

Siemens Innovator3D IC™ is a set of unified solutions for 2.5D/3D IC and chiplet-based design. Innovator3D IC Integrator connects early system exploration, planning, 3D design and implementation, multiphysics analysis, and multi-die signoff, enabling teams to design, validate, and optimize 3D IC systems from concept to silicon.

Siemens’ Innovator3D IC solutions support 3D IC and chiplet-based designs through a unified, system-driven platform that connects architecture, design, analysis, verification, and test across the full multi-die system. It enables early STCO, unified design implementation, system-level multiphysics analysis, multi-die verification and signoff, and integrated DFT and yield optimization. By linking these workflows through a consistent 3D digital twin, Innovator3D IC solutions help teams identify risks earlier, optimize system-level PPA, and reduce costly redesign cycles.

Innovator3D IC solutions are built on an open and interoperable ecosystem with broad standards support, including but not limited to 3Dblox (IEEE P3537) for 3D design data exchange, UCIe and BoW for die-to-die interconnectivity, and IEEE 1838 / IEEE 1687 for multi-die test and access. The Innovator3D IC Integrator cockpit supports various design formats such as GDSII, LEF/DEF, Verilog, ODB++, CSV, etc.

The cockpit Innovator3D IC Integrator is designed to augment and integrate with existing design environments. Its open architecture supports standard formats and interoperates with third-party tools, allowing teams to adopt system-level 3D IC capabilities without disrupting established silicon design flows.

Siemens offers best in class package planning and 3D stack validation tools in the 3D IC design workflows. The integrated electrical and reliability workflow support early predictive, in-design and signoff analysis of multi-layer 2.5/3D designs. The test workflows facilitate collaboration between the package/chiplet design teams with the DFT/test teams, leveraging the best-in-class Siemens multi-die DFT tool suite.

3D IC technology offers the system designer nearly unlimited flexibility to partition their design into chiplets each optimized in an IC technology node best suited for each function. The architectural planning and design workflows facilitate collaboration between the system/RTL design teams with the package/chiplet design teams leveraging predictive analysis to efficiently home in on an optimal architecture prior to deploying expensive and time-consuming design implantation on potentially non-optimal or pathological design.

In-design analysis enables the physical design and electrical/reliability analysis teams to validate the design during the implementation phases, catching errors prior to signoff checks run on completion of the physical design thus avoiding rework and related schedule delays. Careful, up front and validated DFT/test workflow enable timely test bring up during the new product introduction (NPI) phase of the program enabling earlier entry to market of semiconductor products.