
Tessent Advanced DFT
Address the challenges of in-system test for today’s complex SoCs and chiplets with market-leading logic and memory test products that combine capabilities in a powerful test flow to ensure total chip coverage.
Create an infrastructure that makes designs more testable. Silicon lifecycle management solutions achieve high-quality test, identify defects and hidden yield limiters and move beyond test into system debug and validation. This ecosystem of tools effectively analyzes data to provide critical system insights that can then be used for in-life monitoring.
Listen as Marc Hutner, Director of Product Management for Tessent Silicon Learning, expounds on the future of SLM. He describes how DFT is no longer used just for test but is instead becoming a functional subsystem for products. He includes a discussion on how SLM is helping to extend the lifetime of a product by understanding the health of the complete system.
Ensure the highest test quality, accelerate yield ramp and improve safety, security and reliability across the silicon lifecycle using best-in-class solutions for design-for-test (DFT), debug and in-life monitoring plus powerful data analytics.