Visualizing complex RTL design
HDL Designer
HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.
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Interactive HDL visualization and creation tools
Whether a team is creating a design from the ground up, or evaluating RTL for reuse, HDL Designer forms a part of a complete design solution for FPGA and ASIC development. Helping engineering teams analyze, create and manage their complex designs.
Our primary motivation in acquiring HDL Designer Series was to gain access to its design entry and visualization tools, which allow us to work at a higher level than just VHDL or Verilog text entry.
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Verification Academy
Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Verification Horizons blog
Insight and updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Verification Horizons
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.