Partner IP - Alphawave Semi

Our IP Partner, Alphawave Semi, is an industry leader in high-speed connectivity IP with 112G and 224G SERDES chip designs across multiple nodes and fabs - enabling faster data transmission and greater reliability with lower power for designs in 7nm, 6nm, 5nm and beyond.

Partner News from Alphawave Semi

Latest News from our IP partner, Alphawave Semi

Chiplet IP on TSMC 3DFabric

Chiplet IP on TSMC 3DFabric

Alphawave Semi tapes out its cutting edge UCIe™ 3D IP on the advanced TSMC (SoIC-X) technology in the 3DFabric platform, marking a significant evolution in the company’s chiplet integration capabilities!

Foundational AI Platform IP

Breakthrough 36G UCIe™ IP Tapeout on TSMC 2nm

One of the First UCIe Die-to-Die IP Subsystem on TSMC’s 2nm Process with CoWoS® Advanced Packaging Technology Delivers 11.8 Tbps/mm Bandwidth Density and a Scalable Path for 64G Die to Die Interconnects

Foundational AI Platform IP

IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink and UEC

Alphawave Semi’s platform of ready-to-integrate subsystem IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink and UEC plus reference chiplet architecture designs will underpin future AI deployments

Phy IP offerings

Pacakaged IC held between two fingers, in front of an IC layout

AlphaCORE PHY IP

AlphaCORE LR MSS SerDes IP is a high-performance, low-power, DSP-based PHY that supports leading edge NRZ and PAM datacenter standards (1 Gbps to 112 Gbps) and protocols such as PCI-Express Gen1-6 and 1/10/25/50/100 Gbps Ethernet.

ApolloCORE PHY IP

ApolloCORE Multi-Standard-Serdes (MSS) IP is optimized for MR & VSR applications. Highly configurable, it supports all leading edge NRZ & PAM data center standards (1 Gbps to 112 Gbps), with 40% power savings vs. leading LR SerDes

AresCORE PHY IP

AresCORE is an extremely low-power, low-latency UCle™ Die-to-Die (D2D) PHY IP for very high bandwidth connections between two die within the same package through short-reach low-loss channels.

PipeCORE PHY IP

Alphawave Semi PipeCORE PHY IP is a high-performance, low-power, PCIe Gen 1 – Gen 6 PHY, capable of operating at 64 Gbps PAM4 PCIe Gen 6 rates. It includes a hardened PMA layer and a soft PCS layer deliverable.

Packaged AMS device held by gloved fingers.

ZeusCORE PHY IP

The ZeusCORE PHY IP is a XLR, Low-Power, Multi Standard SerDes (MSS) IP that is highly configurable, supports all leading NRZ & PAM datacenter standards, and diverse protocols incl. PCie Gen 1-5 and 1/10/25/50/100 Gbps Ethernet.

Controller IP offerings

GammaCORE Controller IP

GammaCORE is a Universal Chiplet Interconnect Express (UCle™ ) Die-to-Die Controller IP
that implements the latest UCIe 1.1 specification and supports UCIe Streaming protocol applications to best enable multi-die applications.

Person typing on laptop at desk with multiple monitors

KappaCORE Controller IP

KappaCORE-64 is a customer-configurable CXL Controller IP that implements the latest CXL 3.0 specification, and when integrated with PipeCORE-64 PCIe PHY. forms a complete CXL solution.

Engineer checking server farm computers.

PiCORE Controller IP

PiCORE-64 is a PCIe Controller IP that implements the latest PCI Express 6.x specification and, when integrated with PipeCORE-64 PCIe PHY, forms a complete PCIe solution.

An artists' depiction of a memory subsystem

HermesCORE HBM3 Controller and PHY IP

Alphawave Semi HBM3 IP Subsystem is the industry’s
first comprehensive solution for integrating high
bandwidth memory into SoCs, delivering the ultimate
in both high-performance and low power consumption.