Catapult High-Level Synthesis Tools

With leading C++ and SystemC support, Catapult offers advanced HLS tools for FPGA, eFPGA, and ASIC. Catapult will accelerate your success with solutions for outstanding Quality of Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage.

HLS & HLV upcoming events HLS & HLV Resource Library

Catapult High-Level Synthesis Solutions

Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.

C++/SystemC Synthesis

A comprehensive HLS flow taking C++ or SystemC as the design input and optimally targeting ASIC, eFPGA or FPGA implementations tuned for frequency and target technology.

Low-Power Solutions

When it comes to early design space exploration, power estimation, and optimizing for low-power ASIC RTL, Catapult generates highly efficient RTL that is optimized with our PowerPro technology under the hood.

A vector graphic of a catapult with labeled parts such as 'Arm', 'Counterweight', and 'Trigger'.

AI Solutions

Catapult AI enhances HLS for accelerated design exploration, quantization analysis and performance, power and area prediction.