Formally verify the correctness of hand-written RTL vs High-Level models in C++ or SystemC using Sequential Logic Equivalence Checking. Even with differences in language, timing, and interfaces, SLEC-System verifies manual RTL with C++/SystemC proving equivalence between C++ and RTL.
When designers move high-level descriptions into RTL, or make power optimizations to RTL, they must know if the result is functionally equivalent to the original. The SLEC engines deliver solutions for manual, High-Level Synthesis (Catapult-generated), and power optimized RTL equivalence checking.
Paired with a range of best-in-class engines, this powerful verification approach enables bug hunting, bounded-check, and full-proof strategies. SLEC is designed to complement typical simulation-based verification, and it is integrated with debug tools like Siemens EDA Visualizer for understanding falsifications.
For the toughest manual formal verification challenges involving complex implementations in hand-coded RTL. SLEC-System delivers capabilities enabling formal proof of design blocks as challenging as double precision floating point multiplication, mult-add and other problems that simply cannot be exhaustively simulated in RTL.
The Catapult High-Level Synthesis (HLS) on-demand training library contains a set of learning paths with modules to introduce engineers to HLS and high-level verification.
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A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
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