Catapult High-Level Synthesis and Verification

Catapult has the broadest portfolio of hardware design solutions for C++ and SystemC-based High-Level Synthesis (HLS). Catapult's physically-aware, multi-VT mode, with Low-Power estimation and optimization, plus a range of leading Verification solutions make Catapult HLS more than just "C to RTL".

HLS & HLV upcoming events HLS & HLV Resource Library

Catapult High-Level Synthesis Solutions

Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.

C++/SystemC Synthesis

A comprehensive HLS flow taking C++ or SystemC as the design input and optimally targeting ASIC, eFPGA or FPGA implementations tuned for frequency and target technology.

Low-Power Solutions

When it comes to early design space exploration, power estimation, and optimizing for low-power ASIC RTL, Catapult generates highly efficient RTL that is optimized with our PowerPro technology under the hood.

A vector graphic of a catapult with labeled parts such as 'Arm', 'Counterweight', and 'Trigger'.

AI Solutions

Catapult AI enhances HLS for accelerated design exploration, quantization analysis and performance, power and area prediction.

Catapult High-Level Verification Solutions

Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.

Catapult Coverage

HLS-aware code coverage including support for statement, branch, condition, expression (FEC) and array access coverage plus SystemVerilog-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

Catapult Formal Verification Tools

Formally find mistakes, ambiguities and problem design issues or user constraint mistakes early in the HLS process. Even with differences in timing, and interfaces, Catapult Formal enables verification and a coverage closure flow.

SLEC System

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.