Catapult High-Level Synthesis & Verification Events

RISC-V: Tailor processors for performance/efficiency. Learn HLS to build & integrate a wake-word inferencing co-processor, comparing power, performance, & area gains in this workshop.

Edge AI needs power efficiency & performance. Balance with custom hardware! Learn how HLS goes from Python to bespoke hardware. Build an AI accelerator for wake-word inference & measure HLS power/performance gains.

Discover how electronics designers can use HLS to deploy customized accelerators. By tailoring the accelerator to specific inferences, it can outperform off-the-shelf GPUs/TPUs, offering reduced energy consumption.

Join us in Munich where peer-delivered technical sessions will be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of expertise.

Join us at our North America event, which is a dedicated environment for exchanging ideas, information and best practices that enable you to lead in your role and achieve success with your customers.

This talk will describe how to use High-Level Synthesis (HLS) to develop customized AI accelerators, targeted at ASIC or FPGA technology. Learn how you can practically deploy AI inferencing in your edge systems.

Embedded systems demand more compute power than processors can provide. Hardware accelerators offer a solution. This session explores HLS, turning C++ into RTL for ASICs/FPGAs, with real-world examples in ML and image processing.

This workshop will cover High-Level Synthesis and its benefits in producing hardware accelerators quickly and accurately. We will cover the step-by-step design and verification of the Wakeword algorithm using HLS.

Explore SoftMax architecture & microarchitecture to balance performance, area, resources for edge inference. Discover agile FPGA design workflows to keep pace with evolving algorithms.

This hands-on session will introduce you to High-Level Synthesis, a technology that converts a C++ function into a hardware implementation. You’ll create a RISC-V co-processor and integrate it into a Rocket Core design.

Discover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word algorithm using HLS.

Join us to explore the capabilities of EDA AI and see what the future holds. We will discuss the grand vision of having a purpose-built centralized EDA AI platform.

This workshop will cover High-Level Synthesis and its benefits in producing hardware accelerators quickly and accurately. We will cover the step-by-step design and verification of the Wakeword algorithm using HLS.

Gain valuable insight into challenges and solutions of deploying ML in hardware. Understand how HLS and hls4ml streamline the development of neural network-based hardware accelerators and is fundamental for the industry's future.

User2User is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.

Learn how to use HLS to convert C++ to RTL for ASIC/FPGA, enabling custom accelerators. Session covers HLS best practices & real-world examples in ML & image processing for embedded systems.

Explore High-Level Synthesis for fast, accurate hardware accelerator creation. We’ll cover RTL design and verification with the Wakeword algorithm and showcase Catapult AI NN, extending HLS to Python for faster AI HW development.

Join us at DVCon US: attend our short workshops, luncheon, papers, and poster sessions. Visit us in booth 301 to learn how Siemens can help you engineer a smarter future faster.

Visit with Siemens EDA to focus on practical applications of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits to improve your own flows.

Visit with Siemens EDA to focus on practical applications of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits to improve your own flows.

Come see Ankur Gupta's keynote: How AI is Redefining Semiconductor Design for the Edge
Tuesday September 10th at 11:15AM

Visit with Siemens EDA to focus on practical applications of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits to improve your own flows.

Visit with Siemens EDA to focus on practical applications of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits to improve your own flows.

This talk will show how HLS can be used to quickly create and assess multiple RTL implementations for an AI accelerator from a single algorithmic description.

Visit Siemens electronic design automation (EDA) experts at DAC 2024, June 23-27, 2024, in San Francisco, California.

Demand for compute power in embedded systems keeps growing. Moving functions to HW accelerators is crucial. HLS automates by converting C++ functions into HW descriptions for ASICs or FPGAs, enhancing efficiency in IP and ML.

Attend our informative tutorial, luncheon, workshops, papers, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.

We will show how HLS can be used to migrate specific functions from the 5G L1 stack from SW into HW. HLS can enable practical 5G deployments that might not otherwise be possible.

This hands-on class will have attendees develop an inferencing accelerator using HLS. Participants will gain an understanding of how to create a bespoke inferencing accelerator and benefits it can bring to an embedded system. 

Discover unparalleled visibility & insights into complex functional behavior of AI SoC from the Tessent Embedded Analytics team at AIHW, plus learn about harnessing the power of RISC-V architecture for ASIC and FPGA-based designs.

Catapult and PowerPro had quite a lot of sessions this year at DAC featuring a session from NVIDIA and another from Telechips. Use the on-demand links below to check out our in-booth presentations.

C.E.A. presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms. 

Telechips designed AXI4 master IP which meets full AXI4 specifications using C++ HLS, providing software-like access to DMA blocks, while achieving high throughput using multiple outstanding and burst.

Managing the Complexity of an HEVC Encoder (Kvazaar) Implementation on FPGA with Catapult HLS

Dr. Panu Sjövall will shed light on how they were able to implement their embedded real-time HEVC intra encoder on HW with Catapult HLS.

This webinar introduces a simple and robust quantization methodology based on value range analysis.

High-Level Synthesis was quite a hot topic at U2U in North America and Europe. Check out all of our 2023 U2U sessions.

At the IP level, an ISP was created within a year using Catapult, a task that would have been impossible using traditional RTL. To reduce dependency on designer experience, we introduced an AI-assisted DSE tool. 

Find out more about the webinar "Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS".

Learn how C++ and SystemC/MatchLib HLS is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL fast & cheap.

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

Learn how you can use High-Level Synthesis to go from Python to synthesizable RTL to deploy a custom AI accelerator faster and easier than you thought possible. 

Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup with increased bandwidth and energy efficiency.

FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem while preserving the detector energy profile's critical info.

5G standards open the world of hardware development to anyone that can build the best, cost-effective products. Catapult, Questa, and Veloce enable integrated, reliable design and verification solutions for 5G system design.

本ウェビナーでは、特別招待講演としてASA Microsystems社、社長、三輪 晴治氏をお迎えし、「日本半導体産業の寿命 ～ 新しい半導体製品をどんどん開発するために何がどうあるべきか ～」と題しまして、お届けいたします。

In this webinar, we will share this new model of data driven hardware design that produces dramatically better hardware and software – tightly optimized for specific applications.

This tutorial will demonstrate HLS algorithm transformation on an example algorithm from a full software implementation to a high performance, efficient implementation with a mix of hardware and software elements.

Overview of what HLS is and how it can be used to create application specific accelerators. It will show how these accelerators can be integrated into a processor-based system from a hardware and software perspective. 

HLS makes a true HW/SW co-design possible by enabling accurate partitioning
exploration and swapping of functionalities between SW and HW accelerator to
optimize bus traffic, memory utilization and processor load.

HLS Adoption for chip design is driven by increasing design & verification complexity and time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design & verification flow.

This talk will explore how HLS can be used to deliver the data needed to make critical design trade-off decisions and cover how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

To understand which Catapult HLS flow is better suited for our needs at JPL-NASA, we implemented Harris Corner Detector image processing core in both untimed C++ and timed SystemC. Lessons learned from each flow will be presented.

This tutorial will approach the question of design quality from a unique perspective.

This workshop will show the example design running at different levels of abstraction, exploring the different verification objectives that can be achieve at each stage of the design process.

Harvard sheds light on their agile algorithm-hardware co-design and co-verification methodology powered by High-Level Synthesis, which enabled them to reduce front-end VLSI design efforts by orders of magnitude.

This session will show how to create different types of accelerators using HLS and how to integrate them into RISC-V processor designs. AI inferencing algorithm and an encryption algorithm will be used as examples.

Deploying an algorithm in hardware requires an understanding of the algorithm and its data dependencies. We’ll describe an automated way to gain these insights from a C++ description with an automated path to RTL though HLS.

Deploying an algorithm in hardware requires an understanding of the algorithm and its data dependencies. We’ll describe an automated way to gain these insights from a C++ description with an automated path to RTL though HLS.

This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques. 

The presentation will give a high-level technical overview of the Catapult HLS platform that you can use in your future projects to speed up your development process.

In this round table, we will discuss some interesting approaches of HW/SW codesign and the pros and cons of those approaches. Hosted by Anoop Saha and Russell Klein from Siemens and joined by Thierry Tambe from Harvard University.

This talk will focus on silicon for the edge, and the design choices that helps deployment of powerful machine learning algorithms on tiny low-cost energy-efficient hardware.

AI is poised to become ubiquitous in embedded systems. Learn how inferencing can be effectively deployed in low power, computationally constrained devices without needing to bring along a really long extension cord.

Keynote covering enabling technologies – from HLS to hardware software codesign, covering the past, present and the future of silicon design process, the disruptions, and the latest technological trends.