Foundry support

GlobalFoundries Inc. (GF) is one of the world’s leading semiconductor manufacturers, offering a unique mix of design, development, and fabrication services for both leading-edge and mainstream technologies. GlobalFoundries is redefining innovation and semiconductor manufacturing by developing and delivering feature-rich process technology solutions that provide leadership performance in pervasive high growth markets. GlobalFoundries and Siemens EDA frequently collaborate on a wide range of projects to enhance the productivity and outcomes of design, verification, and manufacturing processes for their mutual customers.

GlobalFoundries

GlobalFoundries coverage table

✔: certified; REQ: by service request only

[1]: mPower Digital is certified for all technology nodes. Analog is not officially supported by GF but mPower product team may support customers by request.

[2]: Calibre SmartFill is POR (Plan of Record) below 20nm and Dummy Fill above 20nm.

[3]: 45nm process node supports RF SOI CMOS technology specifically.

[4]: 55nm has a DRC+ kit but 65nm does not.

[5]: Calibre PERC deck is available for 55LP PDK only but not for other 65/55nm PDKs.

●: Tech files would be provided by Siemens for those process nodes not certified. Please contact Aprisa product team regarding your requests.

Intel Foundry offers a wide range of manufacturing services to meet your unique product needs, from mask generation to wafer manufacturing to industry-leading sort and test capabilities. Intel’s advanced packaging techniques allow integration of diverse computing engines across multiple process technologies with performance parameters similar to a single die, but with a platform scope that far exceeds the die-size limit of single-die integration. As a global leader in research and development (R&D) and manufacturing, Intel continuously seeks to optimize and deliver industry-leading platform solutions with our customers for every existing and evolving market segment.

Intel Foundry

The Intel Foundry Accelerator - EDA Alliance is committed to establishing an ecosystem for the design and fabrication of next generation system-on-chip (SoCs) manufactured on Intel Foundry leading-edge process technologies. The initiative promotes collaboration between Intel Foundry and its ecosystem partners, with a focus on reducing risk and tackling design barriers while accelerating time-to-market for mutual customers’ products. As part of the alliance, Siemens EDA will collaborate closely with Intel Foundry to optimize its best-in-class IC design tools, flows, and methodologies for Intel’s world-class processes.

Intel Foundry Accelerator - EDA Alliance

Intel Foundry coverage table

✔: certified (as of July 2026)

[*]: xACT was enabled for Parasitic Extraction on Intel Foundry 18A process node but not released to external customers.

Embedded multi-die interconnect bridge (EMIB)

The embedded multi-die interconnect bridge (EMIB) is a small piece of silicon that is embedded in an organic package substrate cavity. It provides a high-speed high-bandwidth die to die interface pathway. Siemens provides a certified design flow from Die/package co-design, Functional verification, Physical Layout, Thermal, SI/PI/EMIR Analysis and Assembly Verification.

Samsung Foundry offers competitive processes, design technologies, IP, and high-volume manufacturing capability for customers with a full suite of advanced process technologies, including integrated package solutions for 3D/2.5D and flexible and efficient cloud-based design environments. As a partner in the Samsung Advanced Foundry Ecosystem (SAFE™) program, Siemens EDA engages in joint projects with Samsung Foundry to enable the advanced platforms and technologies their mutual customers rely on to bring increasingly sophisticated designs to life.

Samsung Foundry

Samsung coverage table

✔: certified (as of July 2026)

[1]: mPower Analog is certified for 4LPP, 14LPU, LL1318GPF, and mPower Digital is certified for 5LPE.

[2]: Calibre SmartFill is POR (Plan of Record) below 20nm and Dummy Fill above 20nm.

●: Tech files would be provided by Siemens for those process nodes not yet certified. Please contact Aprisa product team for your requests.

The Taiwan Semiconductor Manufacturing Company (TSMC) pioneered the pure-play foundry business model. By choosing not to design, manufacture or market any semiconductor products under its own name, the key to TSMC’s success has always been to focus on its customers’ success. TSMC-made semiconductors serve a global customer base that is large and diverse, with a wide range of applications used in a variety of end markets, including smartphones, high performance computing, the Internet of Things (IoT), automotive, and digital consumer electronics.

TSMC

The TSMC EDA Alliance reduces design barriers for customer adoption of TSMC process technologies. As an EDA Alliance partner, Siemens EDA works closely with TSMC's design technology teams to address mutual customer design needs through the enablement of new EDA tool features that align with TSMC advanced process development roadmap, as well as the implementation of TSMC's design methodology in reference flows. Through this collaboration, TSMC and Siemens EDA enable mutual customers to better achieve their PPA target in a shorter period of time.

TSMC EDA Alliance

TSMC coverage table

✔: certified; WIP: work in progress (as of July 2026)

[1]: Calibre SmartFill is POR (Plan of Record) below 20nm and Dummy Fill above 20nm.

[2]: mPower Analog is fully certified while mPower Digital certification is working in progress for the latest process derivative variant.

[3]: Aprisa 2nm support for the latest process derivative variant is early access as of today. Currently working with Tier-1 customers on N2 production tapeouts.

●: Tech files would be provided by Siemens for those process nodes not yet certified. Please contact Aprisa product team for your requests.

IC Packaging workflow certification

Our ongoing collaboration with TSMC has successfully resulted in automated workflow certification for their InFO integration technology that is part of the 3DFabric platform. For mutual customers, this certification allows the development of innovative and highly differentiated end-products using best-in-class EDA software and industry-leading advanced packaging integration technologies.

Our automated InFO_oS and InFO_PoP design workflows are now certified by TSMC. These workflows include Innovator3D IC, HyperLynx DRC, and Calibre nmDRC technologies.

Integrated Fanout (InFO)

As defined by TSMC, InFO is an innovative wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance for various applications, such as mobile, high performance computing, etc.. The InFO platform offers various package schemes in 2D and 3D that are optimized for specific applications.

InFO_oS leverages InFO technology and features higher density 2/2µm RDL line width/space to integrate multiple advanced logic chiplets for 5G networking application. It enables hybrid pad pitches on SoC with minimum 40µm I/O pitch, minimum 130µm C4 Cu bump pitch and > 2X reticle size InFO on >65 x 65mm substrates.

InFO_PoP, the industry's 1st 3D wafer level fan-out package, features high density RDL and TIV to integrate mobile AP w/ DRAM package stacking for mobile application. Comparing to FC_PoP, InFO_PoP has a thinner profile and better electrical and thermal performances because of no organic substrate and C4 bump.

Chip on Wafer on Substrate (CoWoS)

Integrates logic and memory in 3D targeting, AI, and HPC. Innovator3D IC creates, optimizes & manages a 3D model of the entire CoWoS device assembly.​

Wafer on Wafer (WoW)

Innovator3D IC creates, optimizes, and manages a 3D digital twin model that drives detailed design and verification.​

System-on-Integrated-Chips (SoIC)

Innovator3D IC optimizes and manages a 3D digital twin model that drives design and then verification with Calibre technologies.​

Tower Semiconductor offers advanced analog technologies and manufacturing solutions for the forefront of the world’s most exciting and growing arenas, such as automotive, consumer, medical, industrial, and aerospace and defense, among others. Tower Semiconductor specializes in customized analog solutions for manufacturing differentiated products, offering cutting-edge process technologies including radio frequency (RF), high performance analog (HPA), integrated power management, CMOS image sensors (CIS), non-imaging sensors (NIS) and mixed-signal CMOS, as well as micro-electro-mechanical systems (MEMS) capabilities. To complement its advanced technology platforms, the Company also offers design enablement services, providing mature and valuable tools that enable a quick and accurate design cycle.

Tower Semiconductor

✔: certified; REQ: by customer request

[1]: mPower is supported for all nodes by customer request.

United Microelectronics Corporation (UMC) provides high quality hybrid bonding or die and wafers for 3D IC integration.

Leading global semiconductor foundry

Providing high quality IC fabrication services and various specialty technologies to serve all major sectors of the electronics industry.

3D IC Hybrid Bonding Workflow

Provides a foundry design kit for 3D IC assembly verification and parasitic extraction using Innovator3D IC Integrator and Calibre technologies. Read press release for more details.

UMC coverage table

✔: certified; WIP: work in progress; REQ: by service request only

[1]: Calibre SmartFill is POR (Plan of Record) below 20nm and Dummy Fill above 20nm.