Custom IC Verification

Solido generative and agentic AI transforms custom IC design workflows through natural language interactions, delivering significant productivity gains across the Solido Custom IC platform.

Integrated suite of AI-accelerated SPICE, Fast SPICE and mixed-signal simulators designed to help customers dramatically accelerate critical design and verification for next-generation analog, mixed-signal and custom IC designs.

Comprehensive AI-powered design environment for nominal and variation-aware
verification of custom IC circuitry enabling full design coverage in orders-of-magnitude fewer simulations, with the accuracy of brute-force techniques.

Providing fast, accurate library characterization tools powered by machine learning.

Providing the industry's fastest, most comprehensive integrated IP validation solution, providing complete, seamless IP QA from design to tape-out, across all design views and IP revisions.

The world's fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits.

Industry’s fastest mixed-signal simulation for complex IC designs

Industry standard SPICE simulation for HV, RF and safety critical designs

AI technology speeds up Liberty file creation for missing process, voltage, and temperature combinations in intellectual property libraries, combining fast production with quality analysis and timing verification.

Solido Analytics validates memory library files in early process design kits, managing multiple intellectual property releases and detecting issues. Early error detection reduces integration risks.

Siemens Defectsim enhances analog coverage for circuit reliability and performance. This case study demonstrates early defect detection and resolution, improving quality in automotive and consumer electronics applications.

Solido Design Environment enables robust trimming simulations for high-precision circuit validation, offering advanced analysis and visualization capabilities for post-silicon prediction.

Solido Design Environment demonstrates five-sigma process, voltage, temperature, manufacturing, and corn (PVTMC) analysis capabilities.

eNVM IP verification flow combines Symphony Pro, Eldo Premier and Symphony Solido FastSPICE for PCM/eSTM technologies. The automated system manages data, testing and debugging, supporting mixed-level simulation models.

Lotus Microsystems uses Solido Simulation Suite to optimize power converter design, efficiently handling complex parasitic elements and dynamic switching behavior while maintaining precision and reducing simulation time.

Solido DE with PVTMC Verifier optimizes system-on-chip analog block trimming, particularly in non-volatile memory intellectual property, and achieves 7x simulation speedup vs. traditional Monte Carlo.

NXP qualifies Solido Design Environment for automotive IC design using PVTMC and high-sigma verifiers. Statistical flows enable robust analog IP verification to meet six-sigma yield requirements across process corners.

Infineon uses Solido Intellectual Property Validation Suite to verify consistency across design views (Verilog, Liberty, software-defined facility, library exchange format, design exchange format) in automotive chips.

AI-powered quality assurance ensures format consistency and optimizes .lib production. The Solido Validation and Characterization Suite enhances efficiency, reduce iterations and improves quality.

In the development of memory compiler libraries, accurate timing, power analysis and verification are essential for successful tape out, and for this, accurately characterized Liberty values are needed.

For PDK development, Samsung Foundry used Solido LibSPICE and simulation artificial intelligence for batch verification and high-sigma yield analysis, achieving a 6.5x-10x speedup, saving months in cell verification.

We compare brute-force sampling and AI-powered verification. Solido PVTMC Verifier cut simulations 4x, sped time-to-market 12x and identified a rare outlier pre-silicon, showcasing AI's efficiency in semiconductor design.