U2U24 - CICV Track Sessions

The Custom IC Verification Track had a great lineup of customer presented sessions at U2U 2024! If you missed the live event, you can now enjoy featured track recordings from AWS, Microsoft, SiTime, NVIDIA and Allegro.

Featured On-Demand Resources

Custom IC Verification Track user presentations

Two people in lab coats examining electronic components on a workbench

Webinar

Allegro AI-accelerated PMIC verification

Rajiv Damodaran Prabha, Allegro

Learn how Allegro MicroSystems leveraged AI-powered Solido Design Environment and Analog FastSPICE to accelerate power management integrated circuit verification, resulting in an overall reduction in verification time.

Two people sitting at a desk, looking at a laptop screen together

Webinar

Scale custom IC verification workloads with AWS

Azim Siddique, AWS

Watch this session and learn how to leverage AWS cloud capacity for full cloud migration or peak demand expansion for custom integrated circuit verification workloads, and achieve faster time-to-market.

Two people using laptops while sitting on a couch

Webinar

Microsoft IP QA with Solido IP Validation

Martin Sanchez, Microsoft

Learn how Microsoft leverages Solido IP Validation to address IP quality issues early in the design process, saving time and money on potential (ECOs), improving overall IP quality in production and integration flows.

Two people in business attire shaking hands in an office setting

Webinar

SiTime verification acceleration with AFS

Learn how SiTime leverages AFS, Symphony and Solido Design Environment to ensure seamless integration between the analog and digital components and accelerate verification of high precision MEMS based oscillators SoC.

Person wearing VR headset with holographic display of 3D human figure in front

Webinar

NVIDA AI-accelerated library verification

Chengcheng Liu, NVDIA

Learn how NVIDIA leveraged Solido Additive Learning technology to speed up standard cell library verification with Solido Design Environment while maintaining accuracy on verifying a new process design kit (PDK) revision.

A woman with long hair is wearing a white shirt and has a serious expression on her face.

Webinar

Proactive IP validation with Solido crosscheck at ST

Lippika Parwani, STMicroelectronics

Learn how ST leverages Solido Crosscheck within its IP QA infrastructure to manage IP complexity, providing a comprehensive, proactive IP validation solution to improve the quality of silicon and accelerate SoC delivery.

A painting of a man in a suit and tie standing in front of a building.

Webinar

Symphony enablement in ST's SmartPower Technologies

Nicola Malnati, STMicroelectronics

Learn how ST leveraged Symphony and Visualizer to enhance verification throughput for SmartPower Technologies and analyze and debug the interface between analog and digital in an easier and faster way.

Webinar

Using Solido to evaluate stdcell libs at Infineon

Aravind Radhakrishnan Nair, Infineon

Learn how Solido Library Profiler and Generator enable users at Infineon to compare and profile .libs coming from different IP sources so optimal dataset can be chosen, leading to better PPA analysis and shorter design cycles.

A painting of a man with a beard and mustache wearing a white shirt and a black vest.

Webinar

Leveraging Solido Additive Learning for NVM at ST

G Lo Giudice, STMicroelectronics

Learn how ST uses Solido PVTMC Verifier to predict the dispersion of analog parameters over PVT, and Solido Additive Learning to re-use previous results, reducing the number of runs and accelerating the verification phase.

A person is standing in front of a white background, wearing a black shirt and holding a black object in their hand.

Webinar

Silicon creations 3nm PLL design and simulaiton

Pawel Banachowicz, Silicon Creations

Learn how Silicon Creations harnesses Siemens SPICE technology to manage constant growth of design complexity. Highlighting latest performance gains that made 3nm designs possible including simulations results.

A man with a beard and mustache wearing a black shirt and a white collared shirt underneath.

Webinar

LG - accelerating verification of PLLs for wireless

Antti Havulinna, LG

Learn how Siemens SPICE and mixed-signal simulation tools helped LG achieve significant performance and productivity improvements for phase-locked loop (PLL) intellectual property (IP) versus previous solutions.