What’s new in semiconductor packaging 2504

Engineering data management for IC packaging (EDM-P) is a new optional capability that provides check-in/check-out revision control for the i3D and xPD databases. EDM-P also manages the integration “snapshot” file as well as all the design IP source files used to construct a design such as CSV, Verilog, Lef/Def, GDSII and OASIS. Using EDM-P allows design teams to collaborate and track all information and meta-data for ICP Project folders and files. It allows the design team to verify exactly which source files were used in the design before it is taped out to eliminate errors.

i3D now imports and exports 3Dblox files that contain a complete package assembly supporting all three data stages (Blackbox, Lef/Def, GDSII). i3D can also author and edit 3Dblox data enabling it to drive the downstream design, analysis and verification ecosystem. It has a built-in debugger that can identify 3Dblox syntax issues during 3Dblox read, which is very useful when dealing with 3rd party 3Dblox files.

To enable predictive planning and analysis to deliver more actionable results, we have introduced a number of new capabilities such prototyping power and ground planes and the ability to import Unified Power Format (UPF) to enable more accurate SI/PI and thermal analysis. With testing being a major challenge in multi-chiplet heterogeneous integration, we have integrated Tessent's multi-die capability for design for test (DFT) planning.

Designers can now analyze metal density across device and floorplan, enabling the development of bump patterns that minimize warp and stress. Function reports density in numbers as well as in overlayed plots. Designers can adjust precision to trade off accuracy vs speed.

One of the major goals of the new user experience introduced in 2409 was to enhance designer productivity. As part of that, we are introducing AI-driven predictive commands, which learn how a user designs and predicts the command they may want to use next.

As advanced packages get larger, incorporating more Application Specific Integrated Circuit (ASICs), chiplets and High Bandwidth Memory (HBM), the connectivity increases dramatically making it harder for designers to optimize that connectivity for routing. Connectivity optimization was available in the first release of Innovator3D IC, but it soon became clear that designs were outstripping its capabilities. This led to the ground-up design of a new optimization engine that can handle the emerging complexity of designs, including differential pairs.

The existing 3D floorplan view is the easiest way to verify your design's device and layer stackup. It is now easier to visually verify your device assembly with the new z-axis elevation control. This takes into consideration component type, cell shape, stackup layers, orientation and the part stacks definition.

Continued improvement of interactive editing performance in targeted software development scenarios:

• Moving odd angle traces on large nets – Up to 77% faster
• Trace segment movement back toward original location after shove trace – up to 8X faster
• Dragging trace bus that includes huge net shielding traces – up to 2X faster
• Glossing huge net trace – up to 10X faster
• Interactive edits of forced order net on large package design when active clearances are enabled – up to 16X faster

Often detailed analysis, such as 3 Dimensional Electromagnetic (3DEM) modeling, is only required on a specific area of the design. Outputting the entire design is time-consuming and can often be slow. This new capability allows the export of specified layout design areas requiring simulation or analysis, making the exchange of information between layout and HyperLynx more efficient.

Designers can now filter out eDTC components from generated ODB++ files used for substrate fabrication.