Bring proven job scheduling techniques to the hardware emulation domain with an end-to-end solution that streamlines your entire workflow, from design compilation and emulator selection to software and regression testing. Optimize performance and inform planning with detailed reports and emulation-specific metrics that make working in an emulation environment easier than ever.
Achieve higher utilization and increase throughput and simulation cycles by treating emulation resources as schedulable, shared resources, just like regular compute nodes. Orchestrate workflows end-to-end using a rich GUI.
Make hardware emulation easier using familiar scheduling features including fairshare, reservations, limits and preemption. Rely on trusted, fully featured scheduling technology that has been proven in the chip design space.
Optimize hardware resources and inform organizational planning with detailed resource usage monitoring and emulation-specific metrics. Tune and enforce sharing policies with reporting by project, user and team.
Efficiently orchestrate workflows in your hardware emulation environment with comprehensive policy management features including fairshare, limits and preemption, with a solution that supports the complex signaling schemes emulation jobs and testbenches typically require. Promote fair use by enabling users to reserve time blocks on your emulation platform.
Work end-to-end with your choice of emulator environment including Veloce Strato CS, Cadence Palladium and Protium, and Synopsys ZeBu and HAPS, via a user-friendly, web-based GUI.
2 high-value assets being rebranded and we should have in Resource manager prior to launch.
Technical document | Hardware-assisted design environments
