Siemens launched a revolutionary portfolio of design and verification solution called Questa One in 2025.
Questa One includes its flagship simulator called Questa One Sim. It is an indisputable market leader in DFT simulations for complex multi-die SoCs achieving performance gains that are multifold over competition
Questa One Avery VIP is a market leader in verifying cutting edge IP protocols, and it also helps in reducing the turnaround time from verification to emulation
Questa One Stimulus Free Verification augments the total design coverage by using mathematical, stimulus-free analyses to verify complex, high-speed ASIC and FPGA designs
This bundle provides access to a broad spectrum of applications including design creation, requirements tracking, simulation, power, security, equivalence and debug. This includes flagship Questa Prime Sim App, Lint/CDC App, HDL Designer, Requirements Tracer, Power Aware Sim, Check Connect, Verify and Inspect App, Visualizer Debug and more. Finally, this bundle of products also allows users to integrate all their coverage databases in VIQ to see a unified view of total design verification.
Physical register-transfer level (RTL) synthesis for advanced-node designs with Oasys-RTL.
FPGA design and verification – a complete solution comprising HDL design, simulation, hardware/software co-verification and leading FPGA logic and physical synthesis.
Tessent Silicon Test – a complete technology-leading solution for testability analysis, scan, boundary scan and memory test synthesis and automatic test pattern generation
System Modeling – a complete environment for creating and verification of mixed-signal and multilanguage systems, prevalent in aerospace and other industries