Why Tessent Silicon Executable?
Tessent Silicon Executable (TSE) achieves lower cost of test, faster pattern preparation and accelerated debug and diagnosis by using high-speed interfaces and built-in design knowledge.
Reduce cost of test
TSE uses PCIe and USB to achieve higher bandwidth vs. typical digital interfaces, using In-System Test and the Streaming Scan Network (SSN) to provide an integrated, efficient test access mechanism.
Faster pattern preparation
TSE reads patterns written by Tessent Shell directly, eliminating pattern conversion for the tester and 100% pattern re-use at ATE, SLT and bench, producing productivity gains for design to test.
Accelerated debug and diagnosis
TSE fully comprehends and reconfigures the SSN; failing core identification, core re-test and automatically generated Automated Test Equipment fail logs are directly readable by Tessent Diagnosis for rapid analysis.
Optimized for production
The software has been architected for optimal protocol pattern delivery, minimizing overhead with a multi-threaded architecture. Working in partnership with major ATE vendors, it works seamlessly in their tester environments, including support for multi-site.
Supports dynamic variables
Change and capture key pre-defined portions of the test patterns. Ideal for varying on-device parameters and capturing instrument readings. What previously required multiple patterns can now be achieved with parameters applied at test time on the tester, simplifying the design to tester process.
Built-in test methods
TSE comes with the capability to mask OCComp core contribution in SSN status groups, patch pattern data, re-order and remove payloads and mapping failures to core instances with both OCComp and tester compare. All of this can be done from the test program without going back to design for new patterns.
