PowerPro Guided Power Optimization

During the early stage of RTL when functional vectors are available, PowerPro’s micro-architectural and combinational redundancies help users identify, quantify and fix power bugs. PowerPro’s functional analysis engine finds redundant toggles in the design that can lead to wasted power and suggests fixes to gate the source of such redundant toggles or restructure the logic to avoid wasted toggles.

PowerPro’s early design checks are use-case independent checks based on static analysis of the RTL that can be performed very early in the design cycle. By performing power lint on the RTL, low-hanging issues can be caught and fixed upfront. Early design checks include coverage checks that determine how much of the design registers, memories, macros, data operators etc are gated. Integrated Clock Gating or ICG checks allow RTL designer to assess if the existing ICG cells in the design are redundant from a structural or functional standpoint. Additionally, connectivity checks helps users remove unwanted logic that may be floating or unused.

Early design checks run extremely quickly and can be used to develop low-power coding guidelines for design teams. They can easily be extended to regressions and can be helpful in uncovering potential negative impact RTL changes may have on power upfront.

PowerPro’s sequential optimization is based on Siemens EDA’s patented deep sequential analysis engine that performs multi-cycle analysis for registers and memories to find the most optimal enable conditions for clock gating and memory gating. Deep sequential analysis is a combination of an observability analysis engine and a stability analysis engine. The observability analysis engine performs deep sequential analysis on logic whose output is not observable. Stability-based analysis, however, performs deep sequential analysis on logic whose output is stable. Deep sequential analysis traverses multiple cycles to find enable condition that can be applied to gate multiple registers and shut-off the datapath logic driven by those registers, yielding significant gains.

PowerPro’s sequential optimization techniques include clock gating and memory gating. Complete information for each enable condition is provided including the memory or chain of registers it will gate along with its source reference, the exact enable expression that needs to be implemented by RTL designer, its impact in terms of clock gating efficiency improvement, power reduction, area penalty and details on the signals participating in the enable condition like their logic depth, hierarchical depth, number of signals etc.