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Photonic Design Resources

KEY FEATURES

Photonic Design

Create your PIC design with significant productivity improvement using either a schematic driven or layout first design methodology both using automated waveguide routing.

Layout Only Design

  • Create a PIC design in an IC layout editor
  • Using drag and drop or a script driven methodology
  • Use foundry supplied components, user developed or some combination
  • A simulation netlist can be created as input to our photonic simulation partners
slide8 LayoutOnly pic mzm

Simplifying Photonic Layout

  • Simple waveguide creation and editing
  • Automated crossing insertion
  • Precision snapping to optical pins
  • Wave guide to pin checking
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Complete PIC Design Flow

  • Photonic layout verification with Calibre's equation based design rules
  • Photonic simulation is supported though integration with our partners

    • Simulation partners are Optiwave, VPIphotonics and Lumerical
  • Photonic PDKs are available from multiple foundries
  • Scriptable with Python
  • L-Edit Photonics is available on both Linux® and Windows®
slide9 LayoutOnly zoomIn pic mzm zoomIn

Layout Creation

  • Quickly create a ready for simulation PIC layout
  • Place devices, like schematic or individually
  • Autoroute waveguides, targeting the lowest loss
  • Waveguides can also be created manually
  • The user can use foundry supplied devices, user created or some mixture of both
  • Autoroute or manually make the electrical connections
slide14 interferometer sdl layout creation

Routing Directives

  • If loss information is available in the PDK, the router will create the waveguide with the lowest loss
  • The user can apply routing directives to the waveguides

    • Fixed length
    • Same length
slide15 match len

Waveguide Editing

  • Autorouted waveguides can be edited
  • Minor changes are made using stretch handles
  • Larger changes convert the waveguide back to a wire, make the change, and convert back to a waveguide
  • Active device placements can be moved and the waveguide is updated
  • Waveguides are constructed using foundry, user provided or some combination Pcells

Preparing for Verification

  • The waveguides are annotated back to the schematic
  • A new level of hierarchy is created in the original schematic. The waveguide components are oriented identically as they are in the layout
  • Netlist are exported based on the foundry simulation requirements – transistor or photonic specific simulators
  • LVS netlist can also be exported from the schematic
slide17 sch pcell

Layout First

  • Place the optical components
  • Then the components are autorouted or connected manually
  • If a schematic is needed in order to get a netlist for simulation, the schematic is automatically created, It will look identical to the layout
  • Then both simulation and LVS netlists can be exported

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