Siemens EDA events and webinars

See how Tessent MemoryBIST integrates ECC for manufacturing yield gains: ECC bit masking, test escape prevention, and ECC-assisted repair as a standalone or redundancy-paired solution for in-system reliability.

Get specifics on Questa 2026.1: faster regression performance, new debug visibility features, and coverage closure enhancements to tackle growing UVM/SystemVerilog environment complexity.

In this webinar, we’ll show how adaptable add-ons let you extend Xpedition Standard on demand: pre- and post-layout signal integrity analysis (powered by HyperLynx), rigid-flex design, and advanced ECAD–MCAD co-design.

Learn how clock gating strategies with module-based reporting identify cascaded optimization opportunities deep within fan-in and fan-out paths and maximizes watts saved per engineering hour, enabling low-power design.

Learn how PSS language allows you to specify verification intent and use Questa One to create random tests for you; and these can be "realized" to run across various platforms, tools, and verification stages.

Explore SoftMax architecture & microarchitecture to balance performance, area, resources for edge inference. Discover agile FPGA design workflows to keep pace with evolving algorithms.

Discover how Questa One Sim accelerates simulation with ParallelSim technology, built-in PSS, VHDL constraint solver, automated code coverage exclusions, and more for RTL, gate-level simulations, and coverage.

This webinar will introduce the UALink protocol, focusing on its architecture and key features that enable scalable AI systems; then dive into the essential capabilities of Siemens Avery UALink Verification IP.

This webinar will introduce the UALink protocol, focusing on its architecture and key features that enable scalable AI systems; then dive into the essential capabilities of Siemens Avery UALink Verification IP.

Discover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word algorithm using HLS.

Siloed workflows create bottlenecks that slow design cycles and compromise quality. This webinar introduces a new approach to synergistic verification environments using Questa™ Developer/IVE's integrated ecosystem.

Discover how Aprisa AI and the Siemens EDA AI system boost RTL-to-GDS productivity by 10x, compute-time efficiency by 3x, and PPA by 10%, with ML & RL, generative & agentic AI for accelerated learning and EDA workflow automation.

This webinar shows how Questa One Property Assist turns user prompts into optimized LLM prompts, retrieves LLM provided solutions, and presents the best generated SVA properties for the user.

This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes UVM verification by automating the inference of coverage and stimulus, biasing generation to uncovered areas.

Learn how the Questa One DFT Verification solution, combined with Tessent Silicon Lifecycle Solutions delivers an evolution in user experience and performance to address these emerging verification challenges.

Learn how Questa One Sim FX optimizes fault campaigns with fault list optimization and test ranking capabilities, and seamless integration with existing testbench environments, and comprehensive fault analysis capabilities.

Discover how Questa Verification IQ Testplan Author integrates with Application Lifecycle Management tools (Siemens Polarion and Jama) to deliver a collaborative traceability solution that transforms your verification workflow

This session introduced a transformative solution of connected platforms w/data-driven approaches and AI Integration to address challenges faced by inter-dependencies, workforce limitations & efficiency, and quality assurance.

In this webinar, we will explore how functional fault grading enhances defect coverage. Learn the advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.

This session covered Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC; providing comprehensive protocol coverage, scalability, and advanced debug to verify complex designs for next-gen connectivity.

This webinar will delve into the critical role of hardware security verification, outlining why it is essential for protecting modern FPGA designs from RTL through to the FPGA bitstream. Featured: Bitwise by Red Balloon Security

In this webinar, we will explore the power of debugging code and functional coverage while the RTL simulation is still running, and how interactive coverage analysis can lead to significantly faster design and testbench bring-up.

This session will show how to accelerate root cause analysis and reduce debug turnaround with Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based data-driven verification solution.

This session will delve into the advanced features of Avery’s PCIe Gen 7 Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks

This webinar will focus on using SafetyScope throughout the safety design cycle: architectural phase, RTL phase and post-synthesis phase. Demos: FIT and ISO 26262 metrics, what if analysis to reach ASIL B, optimized fault lists.

Debugging testbenches can be a challenge, so this webinar will show capabilities to simplify and accelerate the process such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM topology visualization

This webinar will equip you with comprehensive safety and security compliance methods to tackle current and emerging requirements for FPGA designs using FPGA Equivalence Checking from RTL to the Bitstream.

This session will explore the powerful Smart Regression features within Siemens EDA’s Questa Verification IQ Regression Navigator - a next-generation, collaborative browser-based, AI/ML data-driven verification solution.

This webinar will show the limitations of existing FPU C++ reference model verification vs. an alternative flow using formal property checking to effectively verify FPU designs; ensuring their accuracy and reliability.