Stimulus free verification

A fully automatic formal issue hunting app that finds deeply hidden issues due to common RTL coding errors, Formal Inspection makes it possible to eliminate a wide range of issues without a testbench.

The Connectivity Analysis within Questa One SFV is a fully automated solution for exhaustively verifying static and dynamic connectivity without requiring knowledge of formal or property specification languages.

Questa Increase Coverage is an automatic formal solution for achieving code coverage closure faster, that addresses an incontrovertible fact of verification: some fraction of uncovered code always remains.

The Formal VIP AMBA & OnChip Libraries improve quality and reduce schedules by building protocol and methodology expertise into packages of reusable assertions that support popular industry-standard interfaces.

Questa One SFV Property Verification exhaustively discovers any design errors that can occur, without needing specific stimulus to detect the issue. This ensures that the verified design is issue-free in all legal input scenarios.

The Questa One SFV Register Analysis automates exhaustive verification of control & status register behavior against CSV or IP-XACT register specification.

Security analysis within Questa One SFV is a fully automated solution for exhaustively verifying that only the paths you specify can reach security or safety-critical storage elements.

Questa One SFV RTL Equivalence does automatically compare specification RTL and implementation RTL code blocks using exhaustive formal analysis. No knowledge of formal or property specification languages is required.

X-Sensitivity Analysis within Questa One SFV is an automated solution that exhaustively roots out ‘X’ issues at the RTL-level without a testbench.

The Siemens Questa Equivalent FPGA solution ensures that FPGA implementation flows, such as synthesis and place-and-route optimizations, do not introduce functional errors.

Gap Free verification optimizes quality of digital designs by proving all functionality for all inputs leading to unprecedented low issue escape rates.

High-level design verification with Questa HL-SYC expansion helps eliminate issues before synthesis by starting verification earlier in the flow.

Questa One SFV Trust Analysis employs automated analysis to detect and report vulnerability concerns regarding security.

Ensures the compliance of RISC-V designs with ISA and functional prerequisites, accelerating verification by eliminating the need for testbench creation.

The Questa One SFV FPU analysis significantly minimizes verification workload, ensuring accurate alignment of floating-point implementations with desired outcomes.

The Fault Protection Analysis is a solution based on formal technology, which analyzes faults by injecting them and formally check their outcome for hardware security and safety.

The Questa Post Silicon Debug app leverages formal analysis and property synthesis to rapidly root cause issues in logic deep within an SoC and prove fixes will not break anything else.