Rapidly Explore and Optimize for Power
Catapult accelerates exploring different architecture tradeoffs and estimates the power, performance and area for each HLS solution. Catapult automatically performs fine grained power-saving optimizations aimed at minimizing switching activity in the RTL to deliver the greatest power savings.
Push-Button Estimation and Analysis
Using the HLS testbench configuration already used for Verification, Catapult automatically drives simulation of generated RTL solutions. Captured switching data and technology library enable the embedded PowerPro engine to give designers rapid feedback on the approximate power cost of HLS blocks, enabling exploration and architectural optimization.
Catapult on-demand training
The Catapult High-Level Synthesis (HLS) on-demand training library contains a set of learning paths with modules to introduce engineers to HLS and high-level verification.
High-Level Synthesis and Verification Group
A group to discuss the finer points of design and verification using Siemens EDA HLS and HLV tools. Join the discussion on new topics, features, content and technical experts.
HLSLibs
A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
HLS Design and Verification Blog
Blog covering next generation high-level synthesis (HLS) design and verification methodologies and techniques.
Catapult Support
Access detailed documentation, releases, resources and more.
EDA consulting
Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.