Why Tessent Streaming Scan Network?
Tessent Streaming Scan Network delivers the promise of true hierarchical plug-n-play DFT. By decoupling core-level DFT configuration from chip level DFT resources, the DFT planning and implementation effort is dramatically reduced while simultaneously reducing manufacturing test cost.
Accelerate time-to-market
Realize a 10x productivity gain using simplified chip-level planning. By decoupling core- and chip-level DFT, core-level compression can be optimized without considering other cores or chip-level resources.
Lower test costs
By combining automatic bandwidth tuning and local generation of DFT signals, whitespace in the pattern is virtually eliminated.
Reduce power profile by up to 90%
SSN provides a smoother power profile using staggered shift/capture clocks and better concurrency. Concurrent cores to be tested can be selected programmatically rather than during design without impacting chip-level routing.
How SSN Accelerates Time to Market
A traditional hierarchical scan test approach has specific challenges, which can be drastically improved using a packetized test delivery mechanism. Tessent Streaming Scan Network (SSN) reduces the DFT planning and implementation effort up to 5x using packetized test delivery. See what Pete Orlando has to say about the latest news on Tessent SSN.
The future of Packetized Test
With packetized delivery of test data becoming the industry standard for complex digital semiconductor designs, Geir Eide, Senior Director, Product Management, explains why leading semiconductor companies have adopted Tessent SSN to improve DFT implementation productivity and manufacturing test time.
Users are achieving up to 10 x gain in DFT implementation & productivity, and up to 5 x reduction in test time.
With Tessent Streaming Scan Network technology, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs. SSN significantly reduces the effort needed to make complex designs highly testable.

