Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) and behave as a single device. Tessent Multi-die software delivers comprehensive automation for the highly complex design for test (DFT) tasks associated with these designs.
Dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation integrated circuits (ICs) based on 2.5D and 3D architectures with Tessent Multi-die.
Tessent Multi-die provides a comprehensive DFT automation solution for highly complex tasks associated with 2.5D and 3D IC designs and works seamlessly with Tessent TestKompress, Streaming Scan Network and IJTAG software.
Tessent Multi-die seamlessly integrates with other Tessent products using an integrated Tessent platform.
Faster, simpler DFT enables IC design teams to generate compliant hardware rapidly. DFT technology that keeps pace with multi-dimensional designs allows for quicker test implementation and optimized manufacturing test costs.
Watch as Vidya Neerkundar, Tessent Product Manager, explains how Tessent Multi-die enables fully automated implementation of DFT for designs that scale sideways (2.5D devices), are stacked on top of one another (3D), or combine both configurations and how the architecture for each die can stay independent regardless of what logic needs to be tested within or across the dies.
Explore and deliver product differentiation faster using 3D heterogeneous integration of node and performance-optimized chiplets with Siemens EDA's market-leading 3D IC technology solution.
Facing manufacturing limitations with respect to die sizes? These advanced designs already push current design-for-test solutions to the limits. In this paper, we outline a path to scalable DFT solutions into the third dimension to deliver an affordable and comprehensive answer to this question.
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