With increasing design complexity and a challenging time-to-market, choosing the right solution to achieve optimal PPA and faster turnaround time, is ever more critical for design teams. Aprisa delivers complete support for RTL-to-GDS digital implementation, including physically-aware RTL synthesis.
Aprisa offers key features for RTL-to-GDS digital implementation flows.
Every design has its unique set of performance, power, and area (PPA) targets. Aprisa offers different optimization modes, providing engineering teams with flexible tradeoffs to achieve competitive design PPA. One such mode is PowerFirst for power centric designs. With PowerFirst, implementation starts based on the best power attainable for a given design, then drives towards convergence with best performance, achieving better power for power-centric designs and, without sacrificing performance.
Aprisa’s correlation matches very closely with that of the industry’s standard signoff DRC and STA tools, further improving on the design PPA. Close correlation with signoff starting at implementation eliminates the need for extra guard bands. It also reduces the number of ECO iterations, resulting in a shorter time to signoff closure.
Aprisa reduces the effort required to achieve top-level timing closure from weeks to days. Its patented in-Hierarchy-Optimization (iHO) technology, leverages Aprisa’s unified hierarchical data model to offer fast top-level timing closure without timing re-budgeting or hierarchy flattening. This greatly reduces the effort from designers to close on the top level design, and minimizes the ECO cycles, while eliminating the back and forth between block and top level owners.
John Mitchell, Arm
Realize improved time to market with an optimal system using automated place-and-route solution that understands interconnect designs. Learn how Aprisa helped Arm.
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