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Why Solido Photonics Design?

With the increasing component count in photonic design along with foundry driven simulation methodology changes. Designer productivity must be increased to meet the schedule. Siemens’ photonic automation drives productivity for both the schematic and layout engineers.

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Productivity for the schematic engineer

Designers connect optical components with a single "optical wire" instead of multiple waveguides in the schematic. This streamlined process significantly boosts productivity and enables a rapid handoff to the layout engineer.

Productivity for the layout engineer

Layout engineers place components matching the schematic, then auto-route to minimize loss. Directives for fixed or match lengths replace the manual task of placing, abutting, and sizing multiple waveguide Pcells in one step.

Featured capabilities

Schematic Driven

•Quickly create a schematic of the PIC design

•Place optical devices

•Connect the devices with waveguide wires

•No need to place multiple waveguide components

•Push the completed schematic to layout

slide13 interferometer sch raw

Layout Creation

•Quickly create a ready for simulation PIC layout

•Place devices, like schematic or individually

•Autoroute waveguides, targeting the lowest loss

•Waveguides can also be created manually

•The user can use foundry supplied devices, user created or some mixture of both

•Autoroute or manually make the electrical connections

slide14 interferometer sdl layout creation

Routing Directives

  • If loss information is available in the PDK, the router will create the waveguide with the lowest loss
  • The user can apply routing directives to the waveguides
  • Fixed length
  • Same length
slide14-interferometer-sdl-layout-creation-640x480

Waveguide Editing

  • Auto-routed waveguides can be edited
  • Minor changes are made using stretch handles
  • Larger changes convert the waveguide back to a wire, make the change, and convert back to a waveguide
  • Active device placements can be moved and the waveguide is updated
  • Waveguides are constructed using foundry, user provided or some combination Pcells

Preparing for Verification

•The waveguides are annotated back to the schematic

•A new level of hierarchy is created in the original schematic. The waveguide components are oriented identically as they are in the layout

•Netlist are exported based on the foundry simulation requirements – transistor or photonic specific simulators

•LVS netlist can also be exported from the schematic

slide17 sch pcell

Layout First

•Place the optical components

•Then the components are autorouted or connected manually

•If a schematic is needed in order to get a netlist for simulation, the schematic is automatically created, It will look identical to the layout

•Then both simulation and LVS netlists can be exported

Additional resources

Technical details