Solido Design Environment is a comprehensive simulation environment including artificial intelligence-enabled variation-aware design and verification.
It works on all types of designs, including standard cells, memories, custom analog/digital, and mixed-signal designs.
The industry's leading AI-powered design environment, engineered for the most demanding custom IC verification challenges. It delivers a silicon-proven suite of tools for nominal, variation-aware, and layout-aware analysis and verification, ensuring robust circuit performance, yield and reliability.
•A solution for nominal, variation-aware, and layout-aware analysis and verification
•Supports third-party simulators and design environments for full flexibility
•Multiple use models: GUI or batch mode
“Verification accuracy and turnaround time are key factors in our design flow, as we create the next generation of memory technology. Siemens’ Solido Design Environment software has delivered brute force-accurate variation analysis coupled with powerful and easy-to-use design optimization, which has significantly reduced the time it takes for us to go from initial design to production.”
Mr. Do Chang-Ho, SK hynix Inc
“The Solido Design Environment software is a clear example of how Siemens EDA listens to their users and develops solutions that empower users to achieve better results. Our designers use Solido Design Environment software as their simulation environment when custom designing state-of-the-art, low-noise, high-resolution, ultra-high speed CMOS image sensors for a wide range of applications including cinematography, machine vision, automotive, AR/VR, and more. We have had an outstanding experience with the solution, due to its productivity-boosting design workflows, intuitive results visualization, and excellent user support.”
Sam Bagwell, Forza Silicon (AMETEK, Inc.)
“For STMicroelectronics’ non-volatile memory team, the ability to relate layout insight directly to electrical behavior is critical. Rather than discovering layout dependent effects late in the process, Solido Layout Analyzer brings this analysis earlier into the flow, improving design confidence and helping cut down the time we spend debugging complex design blocks by weeks. We are planning to test and validate the advantages in our on-going design activity.”
Gianbattista Lo Giudice, STMicroelectronics
This paper describes how engineers at GlobalFoundries used the Solido Design Environment (Solido DE) to demonstrate that the SRAM bit-fail counts predicted using the proposed novel method match closely with the silicon data.
